Dear contributor,

Our automatic CI successfully passed with your patch(es). Please find some details below.

In tcwg_bmk-code_speed-cpu2017rate/llvm-arm-master-Oz, after:
  | 711 commits in llvm
  | 6c50e2b2dda1 [SCEV] Don't require NUW at first add when checking A+C1 < (A+C2)<nuw> (#149795)
  | 39b9891fc9ad [RISCV] Make RISCVVPseudo extend Pseudo. NFC (#149785)
  | 0586067cf07b [Flang] Build fix without precompiled headers
  | c3a9e69737c0 [RISCV] Add test coverage for #148084
  | b17f4d3366cd [AggressiveInstCombine] Use AA during store merge (#149992)
  | ... and 706 more commits in llvm

Produces No change:
  | No change

Used configuration :
 Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection.  Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI.
 
 Configuration:
 - Benchmark: SPEC CPU2017
 - Toolchain: Clang + Glibc + LLVM Linker
 - Version: all components were built from their tip of trunk
 - Target: arm-linux-gnueabihf
 - Compiler flags: Oz
 - Hardware: NVidia TK1 4x Cortex-A15
 
 This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain@lists.linaro.org .  In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.

If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.

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The information below contains the details of the failures, and the ways to reproduce a debug environment:



Current build   : https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017rate--llvm-arm-master-Oz-build/155/artifact/artifacts
Reference build : https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017rate--llvm-arm-master-Oz-build/154/artifact/artifacts