Dear contributor,

Our automatic CI successfully passed with your patch(es). Please find some details below.

In tcwg_bmk-code_vect-spec2k6/llvm-arm-master-O3, after:
  | 611 commits in llvm
  | 4e3266fb6e40 [RISCV] Implement load/store support for XAndesBFHCvt (#150350)
  | b0dea47ae613 GOFF: Only register sections within MCObjectStreamer::changeSection
  | 3d9cf92c281b [gn build] Port bfd73a516160
  | d0b5d34ec70b [gn build] Port 3feb6f971577
  | 076d3050f1f8 [RISCV] Merge verifyDagOpCount into addDagOperandMapping in CompressInstEmitter. (#150548)
  | ... and 606 more commits in llvm

Produces No change:
  | No change

Used configuration :
 Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection.  Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI.
 
 Configuration:
 - Benchmark: 
 - Toolchain: Clang + Glibc + LLVM Linker
 - Version: all components were built from their tip of trunk
 - Target: arm-linux-gnueabihf
 - Compiler flags: O3
 - Hardware: <unknown>
 
 This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain@lists.linaro.org .  In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.

If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.

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The information below contains the details of the failures, and the ways to reproduce a debug environment:



Current build   : https://ci.linaro.org/job/tcwg_bmk-code_vect-spec2k6--llvm-arm-master-O3-build/284/artifact/artifacts
Reference build : https://ci.linaro.org/job/tcwg_bmk-code_vect-spec2k6--llvm-arm-master-O3-build/283/artifact/artifacts