Dear contributor,

Our automatic CI successfully passed with your patch(es). Please find some details below.

In bootstrap_build master-aarch64-bootstrap_profiled_lto_lean, after:
  | 48 commits in gcc
  | 3027010d8bcc AArch64: expand extractions of Adv.SIMD registers from SVE as separate insn.
  | a3e97daf1f74 [RISC-V] Fix trivial bootstrap failure on RISC-V
  | 7b3a0f74e45f Fix dr_chain memleak in vectorizable_load
  | 97a7d568f3d7 tree-optimization/122722 - better SLP reduction group discovery
  | c628aeacedc8 testsuite: Add testcase for already fixed PR [PR121519]
  | ... and 43 more commits in gcc

Produces Success:
  | Results changed to
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap_profiled_lto_lean:
  | # FAILED
  | 
  | From
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap_profiled_lto_lean:
  | # FAILED

Used configuration :
 *CI config* tcwg_bootstrap_build master-aarch64-bootstrap_profiled_lto_lean
 *configure and test flags:* none, autodetected on aarch64-unknown-linux-gnu

If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.

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The information below contains the details of the failures, and the ways to reproduce a debug environment:

You can find the failure logs in
 * https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_profiled_lto_lean-build/991/artifact/artifacts/
The full lists of regressions and improvements as well as configure and make commands are in
 * https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_profiled_lto_lean-build/991/artifact/artifacts/notify/

Current build   : https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_profiled_lto_lean-build/991/artifact/artifacts
Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_profiled_lto_lean-build/990/artifact/artifacts