Dear contributor,

Our automatic CI successfully passed with your patch(es). Please find some details below.

In  master-arm, after:
  | 10 commits in gcc
  | 642504b41ce RISC-V: Correct lmul estimation
  | b49f1dad54d openmp: Fix up ICE in lower_omp_regimplify_operands_p [PR121977]
  | 1d0a5e9fcb8 AArch64: Add SME LUTv2 intrinsics
  | 45ddf553534 AArch64: Add SME LUTv2 architecture extension
  | 80e85c627a3 RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for widen-mul
  | ... and 5 more commits in gcc


Used configuration :
 *CI config* tcwg_gnu_cross_check_gcc master-arm
 *configure and test flags:* --target arm-linux-gnueabihf 

If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.

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The information below contains the details of the failures, and the ways to reproduce a debug environment:

You can find the failure logs in *.log.1.xz files in
 * https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-arm-build/2351/artifact/artifacts/00-sumfiles/
The full lists of regressions and improvements as well as configure and make commands are in
 * https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-arm-build/2351/artifact/artifacts/notify/
The list of [ignored] baseline and flaky failures are in
 * https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-arm-build/2351/artifact/artifacts/sumfiles/xfails.xfail

Current build   : https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-arm-build/2351/artifact/artifacts
Reference build : https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-arm-build/2348/artifact/artifacts