diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index c2f4354..50eaa4a 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -10,11 +10,11 @@ In  arm-eabi cortex-m0 soft, after:
   | 5acdeb08eb5 gdb/dwarf: move index unit vectors to .debug_names reader and use them
   | 3e27b49025f gdb/dwarf: remove all_{comp,type}_units views
   | ... and 16 more commits in binutils
-  | 643c5b42e21d c++/modules: Warn for optimize attributes instead of ICEing [PR108080]
-  | 70136bdc76ae c++/modules: Merge PARM_DECL properties from function definitions [PR121238]
-  | b6d4eaa96d20 Daily bump.
-  | aa19c1076f49 PR modula2/121314: quotes appearing in concatenated error strings
-  | 04a1259ffea2 fortran: Evaluate class function bounds in the scalarizer [PR121342]
+  | 643c5b42e21 c++/modules: Warn for optimize attributes instead of ICEing [PR108080]
+  | 70136bdc76a c++/modules: Merge PARM_DECL properties from function definitions [PR121238]
+  | b6d4eaa96d2 Daily bump.
+  | aa19c1076f4 PR modula2/121314: quotes appearing in concatenated error strings
+  | 04a1259ffea fortran: Evaluate class function bounds in the scalarizer [PR121342]
   | ... and 103 more commits in gcc
   | d61692cbd0 Cygwin: bump API version for addition of new/delete wrappers
   | 7d5c55faa1 Cygwin: add wrappers for newer new/delete overloads
@@ -24,11 +24,11 @@ In  arm-eabi cortex-m0 soft, after:
   | 52f0642b075 gdb/dwarf: make .gdb_index reader use its own list of units
   | 5acdeb08eb5 gdb/dwarf: move index unit vectors to .debug_names reader and use them
   | ... and 17 more commits in gdb
-  | 4e06566dbd1 Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into staging
-  | 86bc3a0abf1 target/riscv: Restrict midelegh access to S-mode harts
-  | e443ba03361 target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
-  | 30ef718423e target/riscv: Fix exception type when VU accesses supervisor CSRs
-  | 09ac27a9b59 riscv: Revert "Generate strided vector loads/stores with tcg nodes."
+  | 4e06566dbd Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into staging
+  | 86bc3a0abf target/riscv: Restrict midelegh access to S-mode harts
+  | e443ba0336 target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
+  | 30ef718423 target/riscv: Fix exception type when VU accesses supervisor CSRs
+  | 09ac27a9b5 riscv: Revert "Generate strided vector loads/stores with tcg nodes."
   | ... and 30 more commits in qemu
 
 
diff --git a/notify/results.compare.txt b/notify/results.compare.txt
index 4be7708..b69601d 100644
--- a/notify/results.compare.txt
+++ b/notify/results.compare.txt
@@ -7,8 +7,8 @@ binutils.sum
 gas.sum
 ld.sum
 Comparing:
-REFERENCE:/tmp/gxx-sum1.12859
-CURRENT:  /tmp/gxx-sum2.12859
+REFERENCE:/tmp/gxx-sum1.8672
+CURRENT:  /tmp/gxx-sum2.8672
 
                                              +---------+---------+
 o  RUN STATUS:                               |   REF   |   RES   |