diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index ba01be0..1a37160 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -18,11 +18,11 @@ In  arm-eabi cortex-m0 soft, after:
   | 7a45c8e0302 gdbserver: convert locals to `bool` in captured_main
   | 71166747219 opcodes/x86: make i386_mnem[] static
   | ... and 26 more commits in gdb
-  | 4e06566dbd Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into staging
-  | 86bc3a0abf target/riscv: Restrict midelegh access to S-mode harts
-  | e443ba0336 target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
-  | 30ef718423 target/riscv: Fix exception type when VU accesses supervisor CSRs
-  | 09ac27a9b5 riscv: Revert "Generate strided vector loads/stores with tcg nodes."
+  | 4e06566dbd1 Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into staging
+  | 86bc3a0abf1 target/riscv: Restrict midelegh access to S-mode harts
+  | e443ba03361 target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
+  | 30ef718423e target/riscv: Fix exception type when VU accesses supervisor CSRs
+  | 09ac27a9b59 riscv: Revert "Generate strided vector loads/stores with tcg nodes."
   | ... and 30 more commits in qemu
 
 
diff --git a/notify/results.compare.txt b/notify/results.compare.txt
index 993d727..070f75a 100644
--- a/notify/results.compare.txt
+++ b/notify/results.compare.txt
@@ -1,14 +1,14 @@
 # Comparing directories
 # REFERENCE: base-artifacts/sumfiles
-# CURRENT:   artifacts/sumfiles
+# CURRENT:   artifacts/99-rewrite/artifacts.old/sumfiles
 
 # Comparing 3 common sum files:
 g++.sum
 gcc.sum
 libstdc++.sum
 Comparing:
-REFERENCE:/tmp/gxx-sum1.6873
-CURRENT:  /tmp/gxx-sum2.6873
+REFERENCE:/tmp/gxx-sum1.2109
+CURRENT:  /tmp/gxx-sum2.2109
 
                                              +---------+---------+
 o  RUN STATUS:                               |   REF   |   RES   |