diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index 06c85e58c..d333041a6 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -1,9 +1,8 @@
-Dear contributor, our automatic CI has detected problems related to your patch(es).  Please find some details below.  If you have any questions, please follow up on linaro-toolchain@lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel.
+Dear contributor,
 
-We appreciate that it might be difficult to find the necessary logs or reproduce the issue locally. If you can't get what you need from our CI within minutes, let us know and we will be happy to help.
-
-In CI config tcwg_kernel/llvm-master-aarch64-stable-allmodconfig after:
+Our automatic CI successfully passed with your patch(es). Please find some details below.
 
+In tcwg_kernel/llvm-master-aarch64-stable-allmodconfig, after:
   | 529 commits in binutils,llvm,qemu
   | dd5516bf98f [gdb/python] Reformat missing_debug.py using black
   | a54a99a6e51 Fix build with GCC 7.5
@@ -17,46 +16,52 @@ In CI config tcwg_kernel/llvm-master-aarch64-stable-allmodconfig after:
   | b71b32ba872f [Gisel][AArch64] legalize G_IS_FPCLASS (#72796)
   | 436f5f652b31 [libc][NFC] Remove unused define (#73222)
   | ... and 360 more commits in llvm
-  | b93c4313f2 Merge tag 'pull-riscv-to-apply-20231122' of https://github.com/alistair23/qemu into staging
-  | 2ebe6659ec Merge tag 'seabios-hppa-v13-pull-request' of https://github.com/hdeller/qemu-hppa into staging
-  | 6bca4d7d1f target/riscv/cpu_helper.c: Fix mxr bit behavior
-  | 82d53adfbb target/riscv/cpu_helper.c: Invalid exception on MMU translation stage
-  | a7472560ca riscv: Fix SiFive E CLINT clock frequency
+  | b93c4313f2f Merge tag 'pull-riscv-to-apply-20231122' of https://github.com/alistair23/qemu into staging
+  | 2ebe6659ec9 Merge tag 'seabios-hppa-v13-pull-request' of https://github.com/hdeller/qemu-hppa into staging
+  | 6bca4d7d1ff target/riscv/cpu_helper.c: Fix mxr bit behavior
+  | 82d53adfbb1 target/riscv/cpu_helper.c: Invalid exception on MMU translation stage
+  | a7472560ca5 riscv: Fix SiFive E CLINT clock frequency
   | ... and 99 more commits in qemu
 
-Results changed to
-# reset_artifacts:
--10
-# build_abe binutils:
--9
-# build_kernel_llvm:
--5
-# build_abe qemu:
--2
-# linux_n_obj:
-33460
-# linux build successful:
-all
-
-From
-# reset_artifacts:
--10
-# build_abe binutils:
--9
-# build_kernel_llvm:
--5
-# build_abe qemu:
--2
-# linux_n_obj:
-33460
-# linux build successful:
-all
-
-The configuration of this build is:
-CI config tcwg_kernel/llvm-master-aarch64-stable-allmodconfig
+Produces Success:
+  | Results changed to
+  | # reset_artifacts:
+  | -10
+  | # build_abe binutils:
+  | -9
+  | # build_kernel_llvm:
+  | -5
+  | # build_abe qemu:
+  | -2
+  | # linux_n_obj:
+  | 33460
+  | # linux build successful:
+  | all
+  | 
+  | From
+  | # reset_artifacts:
+  | -10
+  | # build_abe binutils:
+  | -9
+  | # build_kernel_llvm:
+  | -5
+  | # build_abe qemu:
+  | -2
+  | # linux_n_obj:
+  | 33460
+  | # linux build successful:
+  | all
+
+Used configuration :
+ tcwg_kernel/llvm-master-aarch64-stable-allmodconfig
+
+If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.
 
 -----------------8<--------------------------8<--------------------------8<--------------------------
-The information below can be used to reproduce a debug environment:
+
+The information below contains the details of the failures, and the ways to reproduce a debug environment:
+
+
 
 Current build   : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-stable-allmodconfig-build/95/artifact/artifacts
 Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-aarch64-stable-allmodconfig-build/94/artifact/artifacts