diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index b5776c5958..17ac380988 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -1,9 +1,8 @@
-Dear contributor, our automatic CI has detected problems related to your patch(es).  Please find some details below.  If you have any questions, please follow up on linaro-toolchain@lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel.
+Dear contributor,
 
-We appreciate that it might be difficult to find the necessary logs or reproduce the issue locally. If you can't get what you need from our CI within minutes, let us know and we will be happy to help.
-
-In CI config tcwg_kernel/gnu-master-arm-lts-allyesconfig after:
+Our automatic CI successfully passed with your patch(es). Please find some details below.
 
+In tcwg_kernel/gnu-master-arm-lts-allyesconfig, after:
   | 340 commits in binutils,gcc,qemu
   | d95ba7227e2 RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension
   | 832cdeeccb0 RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension
@@ -17,42 +16,48 @@ In CI config tcwg_kernel/gnu-master-arm-lts-allyesconfig after:
   | 26a7e775a20 Daily bump.
   | 6f59f959e75 hppa: Define MAX_FIXED_MODE_SIZE
   | ... and 173 more commits in gcc
-  | b93c4313f2 Merge tag 'pull-riscv-to-apply-20231122' of https://github.com/alistair23/qemu into staging
-  | 2ebe6659ec Merge tag 'seabios-hppa-v13-pull-request' of https://github.com/hdeller/qemu-hppa into staging
-  | 6bca4d7d1f target/riscv/cpu_helper.c: Fix mxr bit behavior
-  | 82d53adfbb target/riscv/cpu_helper.c: Invalid exception on MMU translation stage
-  | a7472560ca riscv: Fix SiFive E CLINT clock frequency
+  | b93c4313f2f Merge tag 'pull-riscv-to-apply-20231122' of https://github.com/alistair23/qemu into staging
+  | 2ebe6659ec9 Merge tag 'seabios-hppa-v13-pull-request' of https://github.com/hdeller/qemu-hppa into staging
+  | 6bca4d7d1ff target/riscv/cpu_helper.c: Fix mxr bit behavior
+  | 82d53adfbb1 target/riscv/cpu_helper.c: Invalid exception on MMU translation stage
+  | a7472560ca5 riscv: Fix SiFive E CLINT clock frequency
   | ... and 99 more commits in qemu
 
-Results changed to
-# reset_artifacts:
--10
-# build_abe binutils:
--9
-# build_abe stage1:
--5
-# build_abe qemu:
--2
-# linux_n_obj:
-33
-
-From
-# reset_artifacts:
--10
-# build_abe binutils:
--9
-# build_abe stage1:
--5
-# build_abe qemu:
--2
-# linux_n_obj:
-33
-
-The configuration of this build is:
-CI config tcwg_kernel/gnu-master-arm-lts-allyesconfig
+Produces Success:
+  | Results changed to
+  | # reset_artifacts:
+  | -10
+  | # build_abe binutils:
+  | -9
+  | # build_abe stage1:
+  | -5
+  | # build_abe qemu:
+  | -2
+  | # linux_n_obj:
+  | 33
+  | 
+  | From
+  | # reset_artifacts:
+  | -10
+  | # build_abe binutils:
+  | -9
+  | # build_abe stage1:
+  | -5
+  | # build_abe qemu:
+  | -2
+  | # linux_n_obj:
+  | 33
+
+Used configuration :
+ tcwg_kernel/gnu-master-arm-lts-allyesconfig
+
+If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.
 
 -----------------8<--------------------------8<--------------------------8<--------------------------
-The information below can be used to reproduce a debug environment:
+
+The information below contains the details of the failures, and the ways to reproduce a debug environment:
+
+
 
 Current build   : https://ci.linaro.org/job/tcwg_kernel--gnu-master-arm-lts-allyesconfig-build/66/artifact/artifacts
 Reference build : https://ci.linaro.org/job/tcwg_kernel--gnu-master-arm-lts-allyesconfig-build/65/artifact/artifacts