diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index c4930ae5f..9ef591908 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -1,44 +1,67 @@
-Dear contributor, our automatic CI has detected problems related to your patch(es).  Please find some details below.  If you have any questions, please follow up on linaro-toolchain@lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel.
-
-We appreciate that it might be difficult to find the necessary logs or reproduce the issue locally. If you can't get what you need from our CI within minutes, let us know and we will be happy to help.
-
-In CI config tcwg_kernel/llvm-master-arm-lts-allyesconfig after:
-
-  | baseline build
-
-Results changed to
-# reset_artifacts:
--10
-# build_abe binutils:
--9
-# build_kernel_llvm:
--5
-# build_abe qemu:
--2
-# linux_n_obj:
-21590
-# linux build successful:
-all
-
-From
-# reset_artifacts:
--10
-# build_abe binutils:
--9
-# build_kernel_llvm:
--5
-# build_abe qemu:
--2
-# linux_n_obj:
-21590
-# linux build successful:
-all
-
-The configuration of this build is:
-CI config tcwg_kernel/llvm-master-arm-lts-allyesconfig
+Dear contributor,
+
+Our automatic CI successfully passed with your patch(es). Please find some details below.
+
+In tcwg_kernel/llvm-master-arm-lts-allyesconfig, after:
+  | 614 commits in binutils,llvm,qemu
+  | 5637daa2064 x86: simplify SAE checking
+  | b67ed458772 gas: update lex_type[] also for .mri directives
+  | b994624fa57 RISC-V: process rs_align_code also when relaxing
+  | 57db1af8bae Automatic date update in version.in
+  | eb53cbeca8c lto: Add a test for PR ld/32083
+  | ... and 22 more commits in binutils
+  | e3ce979f1b3a Revert "[clang] Increase the default expression nesting limit (#104717)"
+  | 002ba17094e8 [RISCV][MC] Name the vector tuple registers. NFC (#102726)
+  | f3d2609af303 [SLP]Improve/fix subvectors in gather/buildvector nodes handling
+  | f142f8afe21b [AMDGPU] Improve uniform argument handling in InstCombineIntrinsic (#105812)
+  | c9b6339ad40c [NFC] Use stable_hash_combine instead of hash_combine (#105619)
+  | ... and 544 more commits in llvm
+  | 407f9a4b12 Update version for v9.1.0-rc3 release
+  | 3472f54522 Merge tag 'pull-loongarch-20240821' of https://gitlab.com/gaosong/qemu into staging
+  | d4f5e5af86 hw/loongarch: Fix length for lowram in ACPI SRAT
+  | f36538b86b Merge tag 'pull-misc-20240821' of https://gitlab.com/rth7680/qemu into staging
+  | ded1db48c9 target/i386: Fix tss access size in switch_tss_ra
+  | ... and 33 more commits in qemu
+
+Produces Success:
+  | Results changed to
+  | # reset_artifacts:
+  | -10
+  | # build_abe binutils:
+  | -9
+  | # build_kernel_llvm:
+  | -5
+  | # build_abe qemu:
+  | -2
+  | # linux_n_obj:
+  | 21590
+  | # linux build successful:
+  | all
+  | 
+  | From
+  | # reset_artifacts:
+  | -10
+  | # build_abe binutils:
+  | -9
+  | # build_kernel_llvm:
+  | -5
+  | # build_abe qemu:
+  | -2
+  | # linux_n_obj:
+  | 21590
+  | # linux build successful:
+  | all
+
+Used configuration :
+ tcwg_kernel/llvm-master-arm-lts-allyesconfig
+
+If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.
 
 -----------------8<--------------------------8<--------------------------8<--------------------------
-The information below can be used to reproduce a debug environment:
+
+The information below contains the details of the failures, and the ways to reproduce a debug environment:
+
+
 
 Current build   : https://ci.linaro.org/job/tcwg_kernel--llvm-master-arm-lts-allyesconfig-build/200/artifact/artifacts
 Reference build : https://ci.linaro.org/job/tcwg_kernel--llvm-master-arm-lts-allyesconfig-build/199/artifact/artifacts
diff --git a/notify/mail-subject.txt b/notify/mail-subject.txt
index f61c3901c..a1942c788 100644
--- a/notify/mail-subject.txt
+++ b/notify/mail-subject.txt
@@ -1 +1 @@
-[Linaro-TCWG-CI] baseline build: Success on arm
+[Linaro-TCWG-CI] 614 commits in binutils,llvm,qemu: Success on arm