diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index ba0138b0e..9bf1e3b22 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -1,6 +1,6 @@
 Dear contributor,
 
-Our automatic CI has detected problems related to your patch(es). Please find some details below.
+Our automatic CI successfully passed with your patch(es). Please find some details below.
 
 In tcwg_kernel/llvm-master-arm-lts-defconfig, after:
   | 660 commits in binutils,llvm,linux,qemu
@@ -22,11 +22,11 @@ In tcwg_kernel/llvm-master-arm-lts-defconfig, after:
   | 08a2117e83e5f riscv: Fix text patching when IPI are used
   | 56b274473d6e7 mm: hugetlb: independent PMD page table shared count
   | ... and 126 more commits in linux
-  | d6430c17d71 Merge tag 'pull-riscv-to-apply-20250119-1' of https://github.com/alistair23/qemu into staging
-  | f04cac4f8f2 hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events
-  | 941f76e2930 target/riscv: Support Supm and Sspm as part of Zjpm v1.0
-  | fa622855eaa hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache
-  | 2d8e8259287 target/riscv: Add Smdbltrp ISA extension enable switch
+  | d6430c17d7 Merge tag 'pull-riscv-to-apply-20250119-1' of https://github.com/alistair23/qemu into staging
+  | f04cac4f8f hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events
+  | 941f76e293 target/riscv: Support Supm and Sspm as part of Zjpm v1.0
+  | fa622855ea hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache
+  | 2d8e825928 target/riscv: Add Smdbltrp ISA extension enable switch
   | ... and 129 more commits in qemu
 
 Produces Success: