diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index 040048007..17e3f9b39 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -16,17 +16,17 @@ In tcwg_kernel/llvm-master-arm-stable-allnoconfig, after:
   | 1e8b65d8cdb3 [clang][bytecode][NFC] Add a FIXME comment for heap allocations (#151700)
   | 89e4d9f905f7 [Flang] Fix crash with parametrized derived types usage (#150289)
   | ... and 917 more commits in llvm
-  | ebbbf3c8df3a Merge v6.15.9
-  | 097aa9a71fd5 Linux 6.15.9
-  | 620255f477a9 ALSA: hda: Add missing NVIDIA HDA codec IDs
-  | 3d0f8670dacf ALSA: hda/tegra: Add Tegra264 support
-  | 8cfa51779b6e spi: cadence-quadspi: fix cleanup of rx_chan on failure paths
+  | ebbbf3c8df3ab Merge v6.15.9
+  | 097aa9a71fd56 Linux 6.15.9
+  | 620255f477a95 ALSA: hda: Add missing NVIDIA HDA codec IDs
+  | 3d0f8670dacf1 ALSA: hda/tegra: Add Tegra264 support
+  | 8cfa51779b6e0 spi: cadence-quadspi: fix cleanup of rx_chan on failure paths
   | ... and 89 more commits in linux
-  | 4e06566dbd Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into staging
-  | 86bc3a0abf target/riscv: Restrict midelegh access to S-mode harts
-  | e443ba0336 target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
-  | 30ef718423 target/riscv: Fix exception type when VU accesses supervisor CSRs
-  | 09ac27a9b5 riscv: Revert "Generate strided vector loads/stores with tcg nodes."
+  | 4e06566dbd1 Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into staging
+  | 86bc3a0abf1 target/riscv: Restrict midelegh access to S-mode harts
+  | e443ba03361 target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
+  | 30ef718423e target/riscv: Fix exception type when VU accesses supervisor CSRs
+  | 09ac27a9b59 riscv: Revert "Generate strided vector loads/stores with tcg nodes."
   | ... and 88 more commits in qemu
 
 Produces Success: